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  2. Media hardware acceleration
  3. Media-engine generations
  4. Intel media-engine generations
  5. Intel Xe-LP media capabilities
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    Intel Xe-LP media capabilities

    Xe-LP-era Intel media paths include AV1 decoding in the documented full-feature implementation, while AV1 encoding belongs to later specified media groups.

    The Xe-LP-era Intel media path is relevant to AV1 source decoding. It should be assessed separately from the ability to create AV1 output.

    For practical matrix interpretation, the pinned Media Driver identifies explicit TGLx and DG1/SG1 groups. TGLx includes its listed Tiger Lake-related platforms; DG1/SG1 identifies the separate listed product group.

    AV1 decode and encode are separate steps

    These selected TGLx entries retain the table's build distinction:

    Configuration row Full-Feature Free-Kernel
    AVC D/E/Es D/E
    HEVC 10-bit D/E/Es D/E
    VP9 10-bit D/E D/E
    AV1 10-bit D Not listed

    The AV1 entry is decode-only in the Full-Feature declaration. The DG1/SG1 AV1 row likewise gives a full-feature decoding declaration rather than an encoder.

    Intel's published hardware reference lists AV1 8/10-bit, 4:2:0 decoding for its stated Xe MAX and 11th-generation-related product scope. These are source-specific references, not a promise for every device carrying a similar graphics label.

    A source can use AV1 while output uses H.264

    An Emby conversion can reconstruct an AV1 source using a supported selected path, prepare its pictures and encode H.264 output.

    That does not require an AV1 encoder. Conversely, selecting AV1 output needs another encoder capability that the displayed TGLx rows do not supply.

    Arc Alchemist introduces an explicitly different AV1 encode declaration in the compared implementation matrix.

    The backend build is part of the result

    The table's AV1 Full-Feature and Free-Kernel cells differ. An installed package therefore needs its actual implementation/build context preserved when comparing an observed query with the source table.

    The device, selected backend, requested source profile and usable output surface describe the route. A profile absent from one implementation's query is not repaired by pointing at another build's row.

    See Also

    • Intel Elkhart Lake and Jasper Lake media capabilities
    • Intel Arc Alchemist media capabilities
    • Intel Quick Sync Video (QSV)
    • VA-API driver backends
    • How to read a hardware codec support matrix

    References

    • Intel Media Driver: Capability matrix snapshot
    • Intel: Published hardware media reference (2024)
    • Intel: Media Driver for VA-API
    • Intel VPL: API and programming documentation
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